Registered user since Wed 14 Sep 2016
Name:Peter Sewell
Affiliation:University of Cambridge
Personal website: http://www.cl.cam.ac.uk/~pes20/
Contributions
2020
DeepSpec
- ARMv8 and RISC-V relaxed memory concurrency
- Sail: ISA semantics, symbolic execution, and axiomatic concurrency for ARMv8-A and RISC-V
- Welcome and brief project overviews
- Cerberus: executable reference semantics and memory object models for ISO and de facto C
- Committee Member in Organizing Committee within the REMS-DeepSpec 2020-track
- Rigorous modelling and proof for system security engineering: verifying whole-ISA security properties of CHERI-{MIPS,RISC-V,ARM}
PLDI 2020-profile
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