Sail: ISA semantics, symbolic execution, and axiomatic concurrency for ARMv8-A and RISC-V
Joint work with Thomas Bauereiss, Brian Campbell, Alastair Reid, Kathryn E. Gray, Robert M. Norton, Prashanth Mundkur, Mark Wassell, Jon French, Christopher Pulte, Shaked Flur, Ian Stark, Neel Krishnaswami, and Peter Sewell
Sail is a custom domain-specific language for ISA semantics, in which we have developed formal models for ARMv8-A, RISC-V, and MIPS, as well as CHERI-based capability extensions for both RISC-V and MIPS. Our model of ARMv8-A is automatically translated from the authoritative Arm-internal architecture specification language (ASL) definitions. All the above models contain enough system-level features to boot various operating systems, including Linux and FreeBSD, and various smaller microkernels and hypervisors.
Using Sail we are able to generate executable emulators for testing and validation, generate theorem prover definitions for Isabelle, HOL4 and Coq, translate into SMT for automatic verification, and also integrate into our RMEM tool for operational relaxed-memory concurrency semantics.
Recently, we have added a symbolic execution tool for Sail specifications, Isla, which allows us to also support axiomatic concurrency models in the style of Alglave and Maranget’s herd7 tool. This allows us to evaluate the allowed relaxed-memory behaviours for tests that span the full range of the instruction-set architecture. For example, we can specify how instruction cache maintenance instructions interact with self-modifying code in a relaxed-memory setting, or other interesting architectural features not well-covered by existing tools.
Github sail: https://github.com/rems-project/sail, and the Sail-ARM https://github.com/rems-project/sail-arm, Sail-RISC-V https://github.com/rems-project/sail-riscv models.
Mon 15 JunDisplayed time zone: Pacific Time (US & Canada) change
07:00 - 09:00
REMS-DeepSpec Session 2REMS-DeepSpec at REMS/DeepSpec live stream
|Sail: ISA semantics, symbolic execution, and axiomatic concurrency for ARMv8-A and RISC-V|
P: Alasdair Armstrong University of Cambridge, Thomas Bauereiss University of Cambridge, Brian Campbell University of Edinburgh, Alastair Reid Google Research, Kathryn E. Gray Facebook, Robert M. Norton University of Cambridge, Prashanth Mundkur SRI International, Mark Wassell University of Cambridge, Jon French University of Cambridge, Christopher Pulte University of Cambridge, UK, Shaked Flur Google, Ian Stark The University of Edinburgh, Neel Krishnaswami Computer Laboratory, University of Cambridge, Peter Sewell University of Cambridge
|ARMv8 and RISC-V relaxed memory concurrency|
P: Shaked Flur Google, P: Christopher Pulte University of Cambridge, UK, Luc Maranget Inria Paris, Will Deacon ARM Ltd., Susmit Sarkar University of St. Andrews, Ben Simner , Jean Pichon-Pharabod University of Cambridge, UK, Jeehoon Kang KAIST, Sung-Hwan Lee Seoul National University, South Korea, Chung-Kil Hur Seoul National University, South Korea, Alasdair Armstrong University of Cambridge, Ohad Kammar University of Edinburgh, Jon French University of Cambridge, Kathryn E. Gray Facebook, Ali Sezgin University of Cambridge, Peter Sewell University of CambridgeFile Attached